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PD -97136A
IRFB4127PBF
HEXFET(R) Power MOSFET
Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free
D
G S
VDSS RDS(on) typ. max. ID
200V 17m: 20m: 76A
G
D
S
TO-220AB
G D S
Gate
Drain
Source
Absolute Maximum Ratings
Symbol
ID @ TC = 25C ID @ TC = 100C IDM PD @TC = 25C VGS dv/dt TJ TSTG
Parameter
Continuous Drain Current, VGS @ 10V Continuous Drain Current, VGS @ 10V Pulsed Drain Current c Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery e Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds (1.6mm from case) Mounting torque, 6-32 or M3 screw
Max.
76 54 300 375 2.5 20 57 -55 to + 175 300 10lbxin (1.1Nxm) 250 See Fig. 14, 15, 22a, 22b,
Units
A W W/C V V/ns C
Avalanche Characteristics
EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy d Avalanche Current c Repetitive Avalanche Energy f mJ A mJ
Thermal Resistance
Symbol
RJC RCS RJA
Parameter
Junction-to-Case j Case-to-Sink, Flat Greased Surface Junction-to-Ambient ij
Typ.
--- 0.50 ---
Max.
0.4 --- 62
Units
C/W
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1
8/28/08
IRFB4127PBF
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG(int)
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
Min. Typ. Max. Units
200 --- --- 3.0 --- --- --- ---
---
Conditions
--- 0.23 17 --- --- --- --- --- 3.0
--- --- 20 5.0 20 250 100 -100 ---
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mAc m VGS = 10V, ID = 44A f V VDS = VGS, ID = 250A A VDS = 200V, VGS = 0V VDS = 200V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd)
Min. Typ. Max. Units
--- 100 30 31 69 17 18 56 22 5380 410 86 360 590 --- 150 --- --- --- --- --- --- --- --- --- --- --- --- S nC
Conditions
VDS = 50V, ID = 44A ID = 44A VDS = 100V VGS = 10V f ID = 44A, VDS =0V, VGS = 10V VDD = 130V ID = 44A RG = 2.7 VGS = 10V f VGS = 0V VDS = 50V = 1.0MHz VGS = 0V, VDS = 0V to 160V h VGS = 0V, VDS = 0V to 160V g
79 --- --- --- --- Turn-On Delay Time --- Rise Time --- Turn-Off Delay Time --- Fall Time --- Input Capacitance --- Output Capacitance --- Reverse Transfer Capacitance --- Effective Output Capacitance (Energy Related)h --- --- Effective Output Capacitance (Time Related)g
ns
pF
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode) c Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- 76 300 A
Conditions
MOSFET symbol showing the integral reverse
G S D
--- --- 1.3 V --- 136 --- ns --- 139 --- --- 458 --- nC TJ = 125C --- 688 --- --- 8.3 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
p-n junction diode. TJ = 25C, IS = 44A, VGS = 0V f TJ = 25C VR = 100V, IF = 44A TJ = 125C di/dt = 100A/s f TJ = 25C
Notes: Repetitive rating; pulse width limited by max. junction temperature. Limited by TJmax, starting TJ = 25C, L = 0.26mH RG = 25, IAS = 44A, VGS =10V. Part not recommended for use above this value . ISD 44A, di/dt 760A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as When mounted on 1" square PCB (FR-4 or G-10 Material). For recom R is measured at TJ approximately 90C
Coss while VDS is rising from 0 to 80% VDSS. mended footprint and soldering techniques refer to application note #AN-994.
2
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IRFB4127PBF
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
1000
TOP VGS 15V 10V 8.0V 7.0V 6.0V 5.5V 5.0V 4.5V
ID, Drain-to-Source Current (A)
100
ID, Drain-to-Source Current (A)
100
BOTTOM
10
BOTTOM
10
1
4.5V
1
0.1
4.5V
0.01 0.1 1
60s PULSE WIDTH Tj = 25C
10 100
60s PULSE WIDTH Tj = 175C
0.1 0.1 1 10 100
VDS , Drain-to-Source Voltage (V)
VDS , Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
1000
3.5
Fig 2. Typical Output Characteristics
RDS(on) , Drain-to-Source On Resistance
VDS = 50V
ID, Drain-to-Source Current()
100
ID = 44A
3.0
60s PULSE WIDTH
VGS = 10V
10
(Normalized)
TJ = 175C
2.5
2.0
TJ = 25C
1
1.5
1.0
0.1 3.0 4.0 5.0 6.0 7.0 8.0
0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180
VGS, Gate-to-Source Voltage (V)
TJ , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
8000
VGS = 0V, f = 1 MHZ Ciss = Cgs + Cgd, Cds SHORTED Crss = Cgd Coss = Cds + Cgd
Fig 4. Normalized On-Resistance vs. Temperature
16
VGS, Gate-to-Source Voltage (V)
ID= 44A 12
VDS = 160V VDS = 100V VDS = 40V
6000
C, Capacitance (pF)
Ciss 4000
8
2000 Coss 0 1 Crss 10 VDS , Drain-to-Source Voltage (V) 100
4
0 0 20 40 60 80 100 120 QG Total Gate Charge (nC)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage
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3
IRFB4127PBF
1000
1000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA LIMITED BY R DS (on) 100sec
ISD , Reverse Drain Current (A)
100
TJ = 175C
100
1msec 10 10msec 1 Tc = 25C Tj = 175C Single Pulse 0.1 1 10
10
TJ = 25C
1
VGS = 0V
0.1 0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4
DC 100 1000
VSD, Source-to-Drain Voltage (V)
VDS , Drain-toSource Voltage (V)
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Fig 7. Typical Source-Drain Diode Forward Voltage
80
Fig 8. Maximum Safe Operating Area
260 Id = 5mA
ID , Drain Current (A)
60
240
40
220
20
200
0 25 50 75 100 125 150 175
180 -60 -40 -20 0 20 40 60 80 100120140160180 TJ , Temperature ( C )
TC , CaseTemperature (C)
Fig 9. Maximum Drain Current vs. Case Temperature
8.0
Fig 10. Drain-to-Source Breakdown Voltage
1000
EAS, Single Pulse Avalanche Energy (mJ)
800
6.0
ID 8.2A 13A BOTTOM 44A
TOP
Energy (J)
600
4.0
400
2.0
200
0.0 0 40 80 120 160 200
0 25 50 75 100 125 150 175
VDS, Drain-to-Source Voltage (V)
Starting TJ, Junction Temperature (C)
Fig 11. Typical COSS Stored Energy
Fig 12. Maximum Avalanche Energy Vs. DrainCurrent
4
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IRFB4127PBF
1
Thermal Response ( Z thJC )
D = 0.50
0.1
0.20 0.10 0.05
J J 1 R1 R1 2 R2 R2 R3 R3 3 R4 R4 C 1 2 3 4 4
0.01
0.02 0.01 SINGLE PULSE ( THERMAL RESPONSE )
Ci= i/Ri Ci i/Ri
Ri (C/W) 0.02 0.083333 0.181667 0.113333
(sec)
0.000019 0.000078 0.001716 0.008764
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.0001 0.001 0.01 0.1
0.001 1E-006 1E-005
t1 , Rectangular Pulse Duration (sec)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
100
Duty Cycle = Single Pulse 0.01
10
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse)
Avalanche Current (A)
0.05 0.10
1
Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C.
0.1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
Fig 14. Typical Avalanche Current vs.Pulsewidth
250
EAR , Avalanche Energy (mJ)
200
TOP Single Pulse BOTTOM 1% Duty Cycle ID = 44A
150
100
50
Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
175
0 25 50 75 100 125 150
Starting TJ , Junction Temperature (C)
PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav
Fig 15. Maximum Avalanche Energy vs. Temperature
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5
IRFB4127PBF
6.0
50
VGS(th) Gate threshold Voltage (V)
ID = 1.0A
5.0
ID = 1.0mA ID = 250A
40
3.0
IRRM - (A)
4.0
30
20 IF = 29A VR = 100V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
2.0
10
1.0 -75 -50 -25 0 25 50 75 100 125 150 175
0
TJ , Temperature ( C )
dif / dt - (A / s)
Fig 16. Threshold Voltage Vs. Temperature
60
Fig. 17 - Typical Recovery Current vs. dif/dt
3000
50
2500
40
2000
30
QRR - (nC)
IF = 44A VR = 100V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
IRRM - (A)
1500
20
1000
10
500
IF = 29A VR = 100V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
0
0
dif / dt - (A / s)
dif / dt - (A / s)
Fig. 18 - Typical Recovery Current vs. dif/dt
3000
Fig. 19 - Typical Stored Charge vs. dif/dt
2500
2000
QRR - (nC)
1500
1000
500
IF = 44A VR = 100V TJ = 125C TJ = 25C 100 200 300 400 500 600 700 800 900 1000
0
dif / dt - (A / s)
6
Fig. 20 - Typical Stored Charge vs. dif/dt
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IRFB4127PBF
D.U.T
Driver Gate Drive
+
P.W.
Period
D=
P.W. Period VGS=10V
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
-
-
+
RG
* * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
VDD
VDD
+ -
Re-Applied Voltage
Body Diode
Forward Drop
Inductor Curent Inductor Current
Ripple 5% ISD
* VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs
V(BR)DSS
15V
tp
DRIVER
VDS
L
RG
VGS 20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 22a. Unclamped Inductive Test Circuit
VDS VGS RG RD
Fig 22b. Unclamped Inductive Waveforms
VDS 90%
D.U.T.
+
- VDD
V10V GS
Pulse Width 1 s Duty Factor 0.1 %
10% VGS
td(on) tr t d(off) tf
Fig 23a. Switching Time Test Circuit
Current Regulator Same Type as D.U.T.
Fig 23b. Switching Time Waveforms
Id Vds Vgs
50K 12V .2F .3F
D.U.T. VGS
3mA
+ V - DS
Vgs(th)
IG
ID
Current Sampling Resistors
Qgs1 Qgs2
Qgd
Qgodr
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Fig 24a. Gate Charge Test Circuit
Fig 24b. Gate Charge Waveform
7
IRFB4127PBF
Dimensions are shown in millimeters (inches)
TO-220AB Package Outline
TO-220AB Part Marking Information
EXAMPLE: T HIS IS AN IRF1010 LOT CODE 1789 AS SEMBLED ON WW 19, 2000 IN T HE AS SEMBLY LINE "C" Note: "P" in as sembly line position indicates "Lead - Free" INT ERNAT IONAL RECT IFIER LOGO AS SEMBLY LOT CODE PART NUMBER
DAT E CODE YEAR 0 = 2000 WEEK 19 LINE C
TO-220AB packages are not recommended for Surface Mount Application. Note: For the most current drawing please refer to IR website at: http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
8
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 08/08
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